1. Field of the Invention
The present invention relates to a semiconductor memory, and, more particularly, to a memory cell architecture which permits a reduction in the pitch of the memory cells thereby increasing the packing density of a memory cell array.
2. Description of the Related Art
The memory cell architecture for semiconductor memories is roughly divided into two types: open bit line architecture and folded bit line architecture. FIG. 1 shows an example of a semiconductor memory which employs the open bit line architecture. In FIG. 1, reference numeral 1 indicates memory cell arrays, 2 a sense amplifier column, 3 a column decoder and 4 row decoders. A hatched area 2' in the sense amplifier column 2 represents a single sense amplifier (the effective area of one sense amplifier circuit). A pair of bit lines connected to one sense amplifier circuit are indicated by BL and BL. In practice, word lines are provided to extend across the bit lines BL and BL, but in FIG. 1, they are not shown. FIG. 2 illustrates a specific operative structure of the memory cell array 1 of the semiconductor memory depicted in FIG. 1. FIG. 2 shows, by way of example, a two cell-one contact structure. Reference numeral 5 designates a contact, 6 a memory cell, 6' a gate portion of a cell transistor, 14 a diffused region and 15 a cell plate. In FIG. 2, only one memory cell 6 is indicated by the broken-line square, but in practice, a cell is formed at each intersection of the word lines and the bit lines. In FIG. 2, each diffused region 14 has formed therein two cell transistors, and the contact which is connected to their drains is disposed between their hatched gate portions 6'. Reference character F indicates feature size used in the design of this example. In this example, the cell plate 15 which serves as an electrode for forming the capacitance of the memory cell 6 (indicated by the broken line) and the word line are formed of the same material through use of a one-layer gate process technique. The widths and the spacing of the contacts 5, the bit and word lines BL and WL, the cell plates 15 and so forth are defined by the feature size F. The spacing of the diffused regions 14 is set to 3F (the minimum spacing) due to limitations on the process for the formation of the isolating region between diffused regions. In other words, the spacing of the diffused regions 14 cannot be made smaller than 3F. The cell pitch x in the direction of the bit line BL and the cell pitch y in the direction of the word line WL, based on the above design criteria, are such as shown in FIG. 2 in which x=7F and y=6F. These values are implemented with the spacing of the diffused regions 14 set to the minimum spacing 3F.
An open bit line architecture, as depicted in FIGS. 1 and 2, is suitable for close packing of memory cell arrays, as compared with the folded bit line architecture described below. With the open bit line architecture, however, a decrease in the minimum pattern width causes an increase in the relative area occupied by the sense amplifier for each circuit. As a result, the pitch of the sense amplifiers creates an obstacle to the formation of high-density memory cell arrays, introducing difficulties in the circuit design and layout of the sense amplifiers.
On the other hand, the folded bit line architecture has widely been employed as an architecture which overcomes the limitations on the pitch of the sense amplifiers. FIG. 3 shows an example of a semiconductor memory utilizing the folded bit line architecture and FIG. 4 is a specific example of folded bit line memory cell architecture. In FIGS. 3 and 4 like parts corresponding to those in FIGS. 1 and 2 are identified by the same reference numerals. In the illustrated example, memory cells, each connected to given word lines, are connected to alternate bit lines, as depicted in FIG. 4. Accordingly, two word lines pass across each memory cell 6 within one cell pitch x in the direction of the bit lines, as indicated by WL1 and WL2. In this example, with respect to the memory cell 6 indicated by the broken line block, the word line WL1 is one that forms the gate portion 6' of the cell transistor, and the word line WL2 is a passing through word line. In this instance, the word line WL2 extends a distance from the contact region related to the memory cell 6 and the other cell and does not overlap the diffused region 14 within one cell pitch so as to prevent the formation of a transistor. In FIG. 4, the spacing of the word lines WL1 and WL2 and the cell plates 15 is defined by the feature size F. Using the same design criteria as that used in Fig. 2, the cell pitch x in the direction of the bit lines and the cell pitch y in the direction of the word lines are 9F and 6F, respectively, clearly indicating that the cell pitch x is larger than in the case of FIG. 2. Accordingly, the folded bit line architecture cannot achieve the high-density memory cell array of FIG. 2.
FIGS. 5 and 6 illustrate folded bit line architectures which are employed when the pitch of the sense amplifiers exceeds the cell pitch y or 2y. In FIGS. 5 and 6, like parts corresponding to those in FIGS. 1 through 4 are identified by the same reference numerals. Reference numeral 7 indicates change-over switches and 13 multiplexers.
In FIG. 5, the sense amplifier columns 2 are disposed on both sides of the memory cell array 1 and the multiplexers 13, having a cell data readout or write control function, are disposed on both sides of the memory cell array 1, each corresponding to one pair of bit lines BL and BL.
In FIG. 6, the change-over switches 7 are disposed on both sides of the memory cell array 1 to selectively connect thereto the bit line pairs BL, BL, and the multiplexer 13 is disposed on only one side of the memory cell array 1, so that a read and a write of cell data are effected through the multiplexer 13 alone.
With the folded bit line architectures shown in Figs. 5 and 6, the sense amplifiers can be arranged at a pitch four times as large as the cell pitch y in the direction of the word lines. As is the case with FIGS. 3 and 4, however, these folded bit line architectures also encounter the problem that the cell pitch x in the direction of bit lines is a barrier to the construction of high-density memory cell arrays.